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| 82555 10/100 mbps lan physical layer interface networking silicon datasheet product features n optimal integration for lower cost solutions integrated 10/100 mbps single chip physical layer interface solution complete 10/100 mbps mii compliance with mdi support full duplex operation in 10 mbps and 100 mbps modes ieee 802.3u auto-negotiation support for 10base-t half and full duplex, 100base-tx half and full duplex, and 100base-t4 configurations parallel detection algorithm for legacy support of non-auto-negotiation enabled link partner integrated 10base-t transceiver with built in transmit and receive filters glueless interface to t4-phy for combination tx/t4 designs with single magnetics glueless support for 4 leds: activity, link, speed, and duplex led function mapping support via mdi low external component count single 25 mhz clock support for 10 mbps and 100 mbps (crystal or oscillator) single magnetics for 10 mbps and 100 mbps operation qfp 100-pin package n performance enhancements flow control support for ieee 802.3x auto-negotiation and bay technologies phy base* scheme adaptive channel equalizer for greater functionality over varying cable lengths high tolerance to extreme noise conditions very low emissions jabber control circuitry to prevent data loss in 10 mbps operation auto-polarity correction for 10base-t software compatible with 82557 drivers n repeater functionality repeater mode operation support for forced speed of 10 mbps and 100 mbps automatic carrier disconnect for ieee 802.3u compliance auto-negotiation enable/disable capability receive port enable function support for 32 configurable addresses narrow analog side (14 mm) for tight packing in repeater and switch designs document number: 666252-004 revision 2.0 march 1998 notice: notice:
82555 networking silicon ii datasheet revision history n low power consumption typical total solution power including all resistors and magnetics: - 275 ma 100base-tx - 230 ma 10base-t - 250 ma auto-negotiation 300 ma maximum total solution power in dte (adapter) mode power-down of 10base-t/100base- tx sections when not in use n added modes for design, testing, and manufacturability test access port (tap) - nand tree - board level functional test (bist) programmable bypass for 4b/5b encoding/decoding and scrambler/ descrambler diagnostic loopback mode revision date revision description jan. 1997 1.0 first external release of the preliminary datasheet apr. 1997 1.1 first release edition mar. 1998 2.0 general editing information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 82555 10/100 mbps lan physical layer interface may contain design defects or errors known as errata which may cause the pr oduct to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtain ed from: intel corporation p.o. box 7641 mt. prospect il 60056-7641 or call 1-800-879-4683. copyright ? intel corporation, 1997 *third-party brands and names are the property of their respective owners. datasheet iii networking silicon 82555 contents 1.0 introduction................................................................................................................ .......... 1 1.1 functional overview ........................................................................................................1 1.2 compliance to industry standards .................................................................................. 1 2.0 architectural overview................................................................................................... 3 2.1 100 mbps mode............................................................................................................... 3 2.2 10 mbps mode................................................................................................................ .4 2.3 media independent interface (mii) .................................................................................. 5 3.0 pin definitions............................................................................................................. ........... 7 3.1 pin types .................................................................................................................. ..... 8 3.2 clock pins ................................................................................................................. ..... 8 3.3 twisted pair ethernet (tpe) pins ................................................................................... 8 3.4 media independent interface (mii) pins ......................................................................... 8 3.5 media access control/repeater interface control pins ................................................. 9 3.6 led pins ................................................................................................................... ...10 3.7 external bias pins ........................................................................................................1 0 3.8 miscellaneous control pins ..........................................................................................11 3.9 power and ground pins ...............................................................................................12 4.0 100base-tx adapter mode operation ..........................................................................13 4.1 100base-tx transmit clock generation .....................................................................13 4.2 100base-tx transmit blocks ......................................................................................13 4.2.1 100base-tx 4b/5b encoder ....................................................................13 4.2.2 100base-tx scrambler and mlt-3 encoder ...........................................14 4.2.3 100base-tx transmit framing ................................................................15 4.2.4 transmit driver ..........................................................................................16 4.3 100base-tx receive blocks .......................................................................................16 4.3.1 adaptive equalizer .....................................................................................17 4.3.2 receive clock and data recovery ............................................................17 4.3.3 mlt-3 decoder, descrambler, and receive digital section......................17 4.3.4 100base-tx receive framing .................................................................17 4.3.5 100base-tx receive error detection and reporting ...............................17 4.4 100base-tx collision detection ..................................................................................17 4.5 100base-tx link integrity and auto-negotiation solution ...........................................18 4.5.1 link integrity...............................................................................................18 4.5.2 auto-negotiation ........................................................................................18 4.5.3 combination tx/t4 auto-negotiation solution...........................................18 4.6 auto 10/100 mbps speed selection ..............................................................................19 4.7 adapter mode addresses ..............................................................................................19 5.0 10base-t functionality in adapter mode ..................................................................21 5.1 10base-t transmit clock generation..........................................................................21 5.2 10base-t transmit blocks ...........................................................................................21 5.2.1 10base-t manchester encoder................................................................21 5.2.2 10base-t driver and filter .......................................................................21 5.3 10base-t receive blocks ............................................................................................21 5.3.1 10base-t manchester decoder................................................................21 5.3.2 10base-t twisted pair ethernet (tpe) receive buffer and filter............21 82555 networking silicon iv datasheet contents 5.3.3 10base-t error detection and reporting ................................................. 22 5.4 10base-t collision detection....................................................................................... 22 5.5 10base-t link integrity ................................................................................................ 22 5.6 10base-t jabber control function .............................................................................. 22 5.7 10base-t full duplex .................................................................................................. 23 6.0 repeater mode ............................................................................................................... ..... 25 6.1 special repeater features............................................................................................ 25 6.2 connectivity................................................................................................................ ... 25 7.0 management data interface.......................................................................................... 27 7.1 mdi frame structure..................................................................................................... 27 7.2 mdi registers............................................................................................................... .28 7.2.1 mdi registers 0 - 7 .................................................................................... 28 7.2.2 mdi registers 8 - 15 .................................................................................. 31 7.2.3 mdi registers 16 - 31 ................................................................................ 31 8.0 auto-negotiation functionality.................................................................................. 35 8.1 description ................................................................................................................. ... 35 8.2 parallel detect and auto-negotiation ............................................................................ 36 9.0 led descriptions ............................................................................................................ .... 39 10.0 reset and miscellaneous test modes....................................................................... 41 10.1 reset ...................................................................................................................... ....... 41 10.2 loopback................................................................................................................... .... 41 10.3 scrambler bypass ......................................................................................................... 41 10.4 test port.................................................................................................................. ...... 41 11.0 electrical specifications and timing parameters .............................................. 43 11.1 absolute maximum ratings .......................................................................................... 43 11.2 general operating conditions ...................................................................................... 43 11.3 dc characteristics ........................................................................................................ 4 3 11.3.1 mii dc characteristics .............................................................................. 43 11.3.2 10base-t voltage/current dc characteristics ........................................ 43 11.3.3 100base-tx voltage/current dc characteristics ................................... 44 11.4 ac characteristics......................................................................................................... 45 11.4.1 mii clock specifications............................................................................. 45 11.4.2 mii timing parameters .............................................................................. 46 11.4.3 repeater mode timing parameters .......................................................... 47 11.4.4 transmit packet timing parameters ......................................................... 48 11.4.5 squelch test timing parameters .............................................................. 48 11.4.6 jabber timing parameters ........................................................................ 49 11.4.7 receive packet timing parameters .......................................................... 49 11.4.8 10base-t normal link pulse (nlp) timing parameters ......................... 50 11.4.9 auto-negotiation fast link pulse (flp) timing parameters .................... 50 11.4.10 reset timing parameters ......................................................................... 51 11.4.11 x1 clock specifications ............................................................................ 51 11.4.12 100base-tx transmitter ac specification .............................................. 52 12.0 82555 package information............................................................................................. 53 datasheet 1 networking silicon 82555 1.0 introduction the 82555 is a highly integrated, physical layer interface solution designed for 10 and 100 mbps ethernet systems based on the ieee 10base-t and 100base-tx specifications. 100base-tx is an ieee 802.3 physical layer specification for use over two pairs of category 5 unshielded twisted pair or type 1 shielded twisted pair cable. 100base-tx defines a signaling scheme not only for 100 mbps, but also provides csma/cd compatibility with the 10 mbps ieee 802.3 10base-t signaling standard. 1.1 functional overview the 82555 is designed to work in two modes: data terminal equipment (dte) for adapters and repeater for hubs and switches. when configured to dte (adapter) mode, the 82555 incorporates all active circuitry required to interface 10/100 mbps ethernet controllers and csma/cd mac components to 10 mbps and 100 mbps networks. in this and other documents the 82555 may be referred to as the dte, physical medium device (pmd), or physical layer medium (plm). it supports a direct glueless interface to intel components such as the 82557 fast ethernet controller. the 82555 also supports the media independent interface (mii) signals as specified in the ieee 802.3u standard. the figure below shows how the 82555 fits into a 10/100 mbps ethernet adapter design. when configured to repeater mode, the 82555 incorporates several features that allow it to function as a class i or mii level repeater. section 6.0, repeater mode on page 25 describes the 82555 in a repeater type of application. 1.2 compliance to industry standards when operating in 100 mbps mode, the 82555 complies with ieee 802.3u 100base-tx specification. the pmd section with the related changes established in 802.3u 100base-tx complies with ansi x3.263:1995 tp-pmd, revision 2.2. when operating in the 10 mbps mode, the 82555 complies with the ieee 802.3 10base-t specification. figure 1. 82555 10/100 mbps ethernet solution controller/mac intel 82555 system bus interface pair 1 pair 2 ma g netics 82555 networking silicon 2 datasheet the 82555 also complies with the ieee 802.3u auto-negotiation and the ieee 802.3x full duplex flow control sections. the mac interface on the 82555 is a superset of the ieee 802.3u media independent interface (mii) standard. datasheet 3 networking silicon 82555 2.0 architectural overview the 82555 is an advanced combination of both digital and analog logic which combine to provide a functional stack between the media independent interface (mii) and the wire through the magnetics. figure 2 shows a general block diagram of the 82555 component. 2.1 100 mbps mode in 100base-tx mode the 82555 digital subsection performs all signal processing of digital data obtained from the analog reception and the data to be driven into the analog transmit subsection. this includes 4b/5b encoding/decoding, scrambling/descrambling, carrier sense, collision detection, link detection, auto-negotiation, data validation, and providing mii to the media access controller (mac). the 82555 supports the ieee defined mii as its mac interface and expects the controller to drive the management data input/output and management data clock signals to perform the management functions. in 100base-tx mode, the analog subsection of the 82555 performs two functions: ? transmit: the 82555 converts a digital 125 mbps stream into mlt-3 format and drives it through the transmit differential pair onto the physical medium. figure 2. 82555 simplified block diagram 82555 networking silicon 4 datasheet ? receive: the 82555 takes receive analog mlt-3 data from the receive differential pair and converts it into a digital 125 mbps stream, recovering both clock and data signals. 2.2 10 mbps mode the 82555 operation in 10base-t mode is similar to the 82555 operation in 100base-tx mode. manchester encoding and decoding is used instead of 4b/5b encoding/decoding and scrambling/ descrambling. in addition, the transmit clock and receive clock (mii clock signals) provide 2.5 mhz instead of 25 mhz. figure 3. 82555 analog logic 4b/5b encoding scrambler serialization mii tx interface nrz to nrzi nrzi to mlt3 4b/5b decoding de-scrambler serial to 5b mii rx interface nrzi to nrz mlt3 to nrzi magnetics module rj-45 connector 12345678 datasheet 5 networking silicon 82555 the 82555 provides a glueless interface to intel components such as the 82557 fast ethernet controller, as well as any mii compatible device. figure 4 shows a schematic-level diagram of the 82557 fast ethernet controller implementation connected to the 82555 using the mii interface. 2.3 media independent interface (mii) the 82555 supports the media independent interface (mii) as its primary interface to the mac. the mii interface is summarized in table 1 . figure 4. intel 82557/82555 solution 82557 flash (optional) eeprom ( optional ) pci bus si g nals 82555 rxd[3:0] rxc rxerr rxdv crs col txd[3:0] txc txen mdc mdio reset table 1. 82555 mii signal name description direction clock reference mii signal supported by the 82555? txc transmit clock from 82555 (adapter mode only) -- yes txd[3:0] transmit data from mac txc yes txen transmit enable from mac txc yes col collision detect from 82555 asynchronous yes crs carrier sense from 82555 asynchronous yes rxc receive clock from 82555 -- yes rxd[3:0] receive data from 82555 rxc yes rxdv receive data valid from 82555 rxc yes rxerr receive error from 82555 rxc yes mdc management data clock from manager -- yes mdio management data input/output from manager mdc yes 82555 networking silicon 6 datasheet txerr transmit error (repeater mode only) from ric txc yes table 1. 82555 mii signal name description direction clock reference mii signal supported by the 82555? datasheet 7 networking silicon 82555 3.0 pin definitions all active digital pins are defined to have transistor-to-transistor logic voltage levels except the x1 and x2 crystal signals. the transmit differential and receive differential pins are specified as analog outputs and inputs, respectively. the figure below show the pin locations on the 82555 component. the following subsections describe the pin functions. figure 5. 82555 pin numbers and labels 82555 networking silicon 8 datasheet pin allocation is based on a 100-lead quad flat package. all pin locations are based on printed circuit board layout and other design constraints. 3.1 pin types 3.2 clock pins 3.3 twisted pair ethernet (tpe) pins 3.4 media independent interface (mii) pins pin type description i this type of pin is an input pin to the 82555. o this type of pin is an output pin from the 82555. i/o this type of pin is both an input and output pin for the 82555. b this pin is used as a bias pin. the bias pin is either pulled up or down with a resistor. the bias pin may also be used as an external voltage reference. symbol pin type name and function x1 56 i crystal input one. x1 and x2 can be driven by an external 25 mhz crystal. otherwise, x1 may be driven by an external mos level 25 mhz oscillator when x2 is left floating. (the crystal should have a tolerance of 50 ppm or better.) x2 55 o crystal output two. x1 and x2 can be driven by an external 25 mhz crystal. otherwise, x1 may be driven by an external mos level 25 mhz oscillator when this pin is left floating. symbol pin type name and function tdp tdn 47 48 o transmit differential pair. these pins send the serial bitstream for transmission on an unshielded twisted pair (utp) cable. the current-driven differential driver can be two-level (10base-t or manchester) or three-level (100base-tx or mlt-3) signals depending on the operating mode. these signals interface directly with an isolation transformer. rdp rdn 33 34 i receive differential pair. these pins receive the serial bitstream from the isolation transformer. the bitstream can be two-level (10base-t or manchester) or three-level (100base-tx or mlt-3) signals depending on the operating mode. symbol pin type name and function rxd3 rxd2 rxd1 rxd0 97 96 95 92 o receive data. in 100 mbps and 10 mbps mode, data is transferred across these four lines one nibble at a time. datasheet 9 networking silicon 82555 3.5 media access control/repeater interface control pins rxc 90 o receive clock. the receive clock may be either 25 mhz or 2.5 mhz depending on the 82555s operating speed (25 mhz for 100 mbps and 2.5 mhz for 10 mbps). the receive clock is recovered directly from incoming data and is continuous into the media access controller (mac). thus, it must be resynchronized in 10 mbps mode at the start of each incoming packet. rxdv 86 o receive data valid. this signal indicates that the incoming data on the rsc[3:0] pins are valid. rxerr 87 o receive error. the rxerr signal indicates to the 82555 that an error has occurred during frame reception. txd3 txd2 txd1 txd0 71 70 69 68 i transmit data. in 100 mbps and 10 mbps mode, data is transferred across these four lines one nibble at a time. txc 60 i/o transmit clock. the transmit clock may be either 25 mhz or 2.5 mhz depending on the 82555s operating speed (25 mhz for 100 mbps and 2.5 mhz for 10 mbps). the transmit clock outputs a continuous clock into the mac that is generated directly from the external clock source in dte (adapter) mode. in repeater mode, the txc is an input signal operating at either 25 mhz or 2.5 mhz depending on the operating speed, which is typically clocked by a receiver interface device. txen 79 i transmit enable. the transmit enable signal indicates to the 82555 that valid data is present on the txd[3:0] pins. txerr 59 i transmit error. the txerr signal indicates to the 82555 that an error has occurred during transmissions of a frame. crs 82 o carrier sense. the carrier sense signal indicates to the 82555 that traffic is present on the link. crs is an asynchronous output signal. col 85 o collision detect. the collision detect signal operates in half duplex mode and indicates to the 82555 that a collision has occurred on the link. col is an asynchronous output signal to the controller. mdio 80 i/o management data input/output. the mdio signal is a bidirectional data pin for the management data interface (mdi). mdc 81 ii management data clock. the mdc signal functions as a clock reference for the mdio signal. mdc should operate at a maximum frequency of 2.5 mhz symbol pin type name and function rxcong 77 i receive congestion. if the following conditions exist, the rxcong is an active high and indicates an overrun on the controller receive side: ? full duplex phy base (bay technologies) flow control dte (adapter) mode ? full duplex signal (fdx_n) is high ? full duplex technology is active through auto-negotiation porten 76 i port enable. in repeater mode when the porten signal is low, the following signals will be tri-stated: rxd[3:0], rxc, rxdv, and rxerr. symbol pin type name and function 82555 networking silicon 10 datasheet 3.6 led pins 3.7 external bias pins note: the resistor values described for the external bias pins are only recommended values and may require to be fine tuned for various designs. txrdy (tout) 4 o this pin is multiplexed and can be used for one of the following: transmit ready. if full duplex and phy base (bay technologies) flow control modes are enabled, the txrdy signal enables transmission while it is asserted. tout. when the test enable signal is activated, this signal functions as the test output port. fdx_n 5 i/o full duplex. in dte (adapter) mode, this active low output signal reports the result of the duplex configuration to the mac. this pin can also operate as the led driver and will be an active low for all technologies. in repeater mode, this signal is used for auto-negotiation advertisement to the 82555s link partner and activates the phy base (bay technologies) flow control if 100base-tx full duplex is the highest common technology between the 82555 and its link partner. symbol pin type name and function actled 12 o activity led. this signal indicates either transmit or receive activity. when activity is present, the actled is on. when no activity is present, the actled is off. liled 11 o link integrity led. this signal indicates the link integrity. if a valid link is present in either 10 mbps or 100 mbps, the liled is on; and if an invalid link is preset, liled is off. for a combination design board, the liled should be connected to the tx technology led. speed- led 13 o speed led this signal is used to indicate the speed of operation. for 100 mbps, the speedled will be on; and for 10 mbps, the speedled will be off. symbol pin type name and function rbias100 44 b bias reference resistor 100. a 634 w resistor should be connected from this pin to ground. rbias10 43 b bias reference resistor 10. a 768 w resistor should be connected from this pin to ground. pd1 42 i pull down one. a 10 k w resistor should be connected from this pin to ground. pd2 100 i pull down one. a 1 k w resistor should be connected from this pin to ground. symbol pin type name and function datasheet 11 networking silicon 82555 3.8 miscellaneous control pins symbol pin type name and function reset 1 i reset. the reset signal is active high and resets the 82555. a reset pulse width of at least 1 m s should be used. frc100 (mactyp) 51 i this pin is multiplexed and can be used for one of the following: force 100/10 mbps. in repeater mode, this pin configures the repeater to either 100 mbps (active high) or to 10 mbps (active low). mac type. in dte (adapter) full duplex mode, if this input signal is high, the 82555 drives 82557 mode. if this input signal is low, the 82555 drives a generic mii mac mode. phya4 (tin) 22 i this pin is multiplexed and can be used for one of the following: phy address 4. in repeater mode, this signal represents the fifth bit for address port configuration. tin. if the test enable signal is active, this signal is used as the test input data. phya3 (slvtri) 52 i/o this pin is multiplexed and can be used for one of the following: phy address 3. in repeater mode, this signal represents the fourth bit for address port configuration. slave tri-state. in dte (adapter) mode, this output operates in conjunction with the t4 advanced signal. when both are active, the slave phy is inactive and tri-states all its outputs. phya2 (listat) 6 i this pin is multiplexed and can be used for one of the following: phy address 2. in repeater mode, this signal represents the third bit for address port configuration. link status. in dte (adapter) mode, if t4 advance is active, the listat_n signal is active low and the slave phy link is valid. phya1 (texec) 25 i this pin is multiplexed and can be used for one of the following: phy address 1. in repeater mode, this signal represents the second bit for address port configuration. test execute. if test enable is asserted, this signal acts as the test execution command indicating that the pin 22 is being used as the test input pin. phya0 (tck) 24 i this pin is multiplexed and can be used for one of the following: phy address 0. in repeater mode, this signal represents the first bit for address port configuration. test clock. if test enable is asserted, this signal acts as the test clock signal. andis (t4adv) 54 i this pin is multiplexed and can be used for one of the following: auto-negotiation disable. in repeater mode, the auto-negotiation operates for management reasons. if this input signal is high, the auto-negotiation operation will be disabled. t4adv. in dte (adapter) mode, this pin enables the combo mode. this allows the listat and slvtri pins to be used as interface to the slave phy. scrmby 23 i scrambler/descrambler bypass. if scrmby is high, the scrambler/ descrambler of tp-pmd will be bypassed. lpbk 2 i loopback. when the lpbk signal is high, the 82555 will perform a diagnostic loopback function. rpt 50 i repeater. when the rpt signal is high, the 82555 functions in repeater mode. when this signal is low, the 82555 runs in dte (adapter) mode. testen 21 i test. if the testen signal is high, the 82555 enables the test ports. 82555 networking silicon 12 datasheet 3.9 power and ground pins symbol pin type name and function vcc 7, 9, 15, 17, 19, 27, 29, 31, 36, 38, 40, 45, 58, 62, 64, 66, 73, 75, 83, 88, 93, 98 i power: +5 v 5% vss 3, 8, 10, 14, 16, 18, 20, 26, 28, 30, 32, 35, 37, 39, 41, 46, 49, 53, 57, 61, 63, 65, 67, 72, 74, 78, 84, 89, 91, 94, 99 i ground: 0 v datasheet 13 networking silicon 82555 4.0 100base-tx adapter mode operation 4.1 100base-tx transmit clock generation a 25 mhz crystal or a 25 mhz oscillator is used to drive the 82555s x1 and x2 pins. the 82555 derives its internal transmit digital clocks from this crystal or oscillator input. the transmit clock signal is a derivative of the 25 mhz internal clock. the accuracy of the external crystal or oscillator must be 0.0005% (50 ppm). 4.2 100base-tx transmit blocks the transmit subsection of the 82555 accepts nibble-wide data on the txd[3:0] lines when txen is asserted (high). the transmit subsection passes data unconditionally to the 4b/5b encoder as long as txen is active. the 4b/5b encoder accepts nibble-wide data (4 bits) from the mac and compiles it into 5-bit-wide parallel symbols. these symbols are scrambled and serialized into a 125 mbps bit stream, converted by the analog transmit driver into a mlt-3 waveform format, and transmitted onto the unshielded twisted pair (utp) or shielded twisted pair (stp) wire. 4.2.1 100base-tx 4b/5b encoder the 4b/5b encoder complies with the ieee 802.3u 100base-tx standard. four bits are encoded according to the transmit 4b/5b lookup table. the lookup table matches a 5-bit code to each 4-bit code. the table below illustrates the 4b/5b encoding scheme associated with the given symbol. table 2. 4b/5b encoder symbol 5b symbol code 4b nibble code 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 a 10110 1010 b 10111 1011 c 11010 1100 d 11011 1101 82555 networking silicon 14 datasheet 4.2.2 100base-tx scrambler and mlt-3 encoder data is scrambled in 100base-tx in order to reduce electromagnetic emissions during long transmissions of high-frequency data codes. the scrambler logic accepts 5 bits from the 4b/5b encoder block and presents the scrambled data to the mlt-3 encoder. the 82555 implements the 11-bit stream cipher scrambler as adopted by the ansi xt3t9.5 committee for utp operation. the cipher equation used is: x[n] = x[n-11] + x[n-9] (mod 2) the mlt-3 encoder receives the scrambled non-return to zero (nrz) data stream from the scrambler and encodes the stream into mlt-3 for presentation to the driver. mlt-3 is similar to nrzi coding, but three levels are output instead of two. there are three output levels: positive, negative and zero. when an nrz 0 arrives at the input of the encoder, the last output level is e 11100 1110 f 11101 1111 i 11111 inter packet idle symbol (no 4b) j 11000 1st start of packet symbol 0101 k 10001 2nd start of packet symbol 0101 t 01101 1st end of packet symbol r 00111 2nd end of packet symbol and flow control v 00000 invalid v 00001 invalid v 00010 invalid v 00011 invalid h 00100 invalid v 00101 invalid v 00110 invalid v 01000 invalid v 01100 invalid v 10000 flow control s v 11001 invalid table 2. 4b/5b encoder symbol 5b symbol code 4b nibble code datasheet 15 networking silicon 82555 maintained (either positive, negative or zero). when an nrz 1 arrives at the input of the encoder, the output steps to the next level. the order of steps is negative-zero-positive-zero which continues periodically. the figure below illustrates this process. 4.2.3 100base-tx transmit framing the 82555 does not differentiate between the fields of the mac frame containing preamble, start of frame delimiter, data and cyclic redundancy check (crc). when txen is asserted, the 82555 accepts data on the mii txd[3:0] lines, encodes it, and sends it out onto the wire. the 82555 encodes the first byte of the preamble as the jk symbol, encodes all other pieces of data according to the 4b/5b lookup table, and adds the tr code after the end of the packet (de- assertion of txen). the 82555 scrambles and serializes the data into a 125 mbps stream, encodes it as mlt-3, and drives it onto the wire. if txerr is asserted during transmission of valid data, the 82555 transmits an invalid h symbol. figure 6. nrz to mlt-3 encoding diagram clock nrz nrz1 mlt-3 1100 0 11 0 1100 0 11 0 1100 0 11 0 82555 networking silicon 16 datasheet 4.2.4 transmit driver the transmit differential lines are implemented with a digital slope controlled current driver that meets the tp-pmd specifications. current is sunk from the isolation transformer by the transmit differential pins. the conceptual transmit differential waveform for 100 mbps is illustrated in the following figure. the magnetics module that is external to the 82555 converts i tdp and i tdn to 2.0 v pp , as required by the tp-pmd specification. the same magnetics used for 100base-tx mode should also work in 10base-t mode. the following is a list of current magnetics modules available from several vendors: 4.3 100base-tx receive blocks the receive subsection of the 82555 accepts 100base-tx mlt-3 data on the receive differential pair. due to the advanced digital signal processing design techniques employed, the 82555 will accurately receive valid data from category 5 (cat5) utp and type 1 stp cable of length well in excess of 100 meters. figure 7. conceptual transmit differential waveform (v tdp -v tdn ) +1v 0v -1v 40ma i tdp 20ma 0 40ma 20ma 0 i tdn t t t table 3. magnetics modules vendor model/type 100base-tx 10base-t delta lf8200a yes yes pulse engineering pe-68515 yes yes pulse engineering h1012 yes yes datasheet 17 networking silicon 82555 4.3.1 adaptive equalizer the distorted mlt-3 signal at the end of the wire is restored by the equalizer. the equalizer performs adaptation based on the shape of the received signal, equalizing the signal to meet superior data dependent jitter performance. 4.3.2 receive clock and data recovery the clock recovery circuit uses advanced digital signal processing technology to compensate for various signal jitter causes. the circuit recovers the 125 mhz clock and data and presents the data to the mlt-3 decoder. 4.3.3 mlt-3 decoder, descrambler, and receive digital section the 82555 first decodes the mlt-3 data; afterwards, the descrambler reproduces the 5b symbols originated in the transmitter. the descrambling is based on synchronization to the transmit 11-bit linear feedback shift register (lfsr) during idle. the data is decoded at the 4b/5b decoder. once the 4b symbols are obtained, the 82555 outputs the receive data to the csma unit. 4.3.4 100base-tx receive framing the 82555 does not differentiate between the fields of the mac frame containing preamble, start of frame delimiter, data and crc. during 100 mbps reception, the 82555 differentiates between the idle condition ("l" symbols on the wire) and the preamble or start of frame delimiter. when two non-consecutive bits are 0b within 10 bits (125 mbps 5b data coding) the 82555 immediately asserts the crs signal. when the jk symbols (11000, 10001) are fully recognized, the 82555 asserts the rxdv signal and provides the data received on the mii rxd[3:0] to the receive clock. if the jk symbol is not recognized (false carrier sense), the crs signal is immediately de- asserted and rxerr is asserted. otherwise, the valid data is passed through the mii until the 82555 finds the tr (01101, 00111) and idle symbols in order to de-assert txdv and crs. 4.3.5 100base-tx receive error detection and reporting in 100base-tx mode, the 82555 can detect errors in receive data in a number of ways. any of the following conditions is considered an error: ? link integrity fails in the middle of frame reception. ? the start of stream delimiter jk symbol is not fully detected after idle. ? an invalid symbol is detected at the 4b/5b decoder. ? idle is detected in the middle of a frame (before tr is detected). when any of the above error conditions occurs, the 82555 immediately asserts the receive error signal to the mac. the rxerr signal is asserted as long as the receive error condition persists on the receive pair. 4.4 100base-tx collision detection 100base-tx collisions in half duplex mode only are detected similarly to 10base-t collision detection, via simultaneous transmission and reception. 82555 networking silicon 18 datasheet 4.5 100base-tx link integrity and auto-negotiation solution the 82555s auto-negotiation function automatically configures the device to the technology, media, and speed to operate with its link partner. auto-negotiation is widely described in ieee specification 802.3u, clause 28. the 82555 supports 10base-t half duplex, 10base-t full duplex, 100base-tx half duplex, and 100base-tx full duplex. the 82555 has two physical medium attachment (pma) technologies with its link integrity function, 10base-t and 100base-tx. the 82555 also has a special interface defined between itself and a phy-t4 in order to implement an auto-negotiation combination card. 4.5.1 link integrity in 100base-tx, the link integrity function is determined by a stable signal status coming from the tp-pmd block. signal status is asserted when the pmd detects breaking squelch energy and the right bit error rate according to the ansi specification. 4.5.2 auto-negotiation the 82555 fully supports ieee 802.3u, clause 28. in dte (adapter) mode, the technology, 10base-t or 100base-tx, is determined by the auto-negotiation result. in repeater mode only, this function can be disabled by pin configuration. if the t4adv pin is active, the auto- negotiation function will advertise and negotiate t4 technology. speed and duplex auto-select are functions of auto-negotiation. however, these parameters may be manually configured via the mii management interface (mdi registers). 4.5.3 combination tx/t4 auto-negotiation solution the auto-negotiation function is available in both the 82555 and a phy-t4. for these phys to operate together, some arbitration at the pma level is required and the auto-negotiation function of one of the phys must be disabled. for this purpose, the 82555 is defined as the master; and the phy-t4, the slave. in combination mode, only the 82555s auto-negotiation function is enabled (the phy-t4s auto-negotiation is disabled). in a combination board, a phy-t4 is used only to support 100base-t4 operation and the 82555 is sued to support 100base-tx full or half duplex and 10base-t full or half duplex as determined by the auto-negotiation or parallel detection function. combination mode is available only in dte (adapter) mode with the following pin interface: ? t4adv (pin 54): enables t4 technology in a phy-tx auto-negotiation system. ? slvtri (pin 52): disables the phy-t4.the phy-t4 is enabled only if the t4 technology has been detected by auto-negotiation or parallel detection. ? listat (pin 6): indicates valid link on the phy-t4. when slvtri is de-asserted, the phy- t4 should be active. datasheet 19 networking silicon 82555 the figure below illustrates an 82557/82555/phy-t4 solution in a block diagram. 4.6 auto 10/100 mbps speed selection the mac may either allow the 82555 to automatically select its operating speed or force the 82555 into 10 mbps or 100 mbps mode. the management data interface (mdi) can control the 82555 speed mode. the 82555 autoselect function determines the operation speed of the media based on the link integrity pulses it receives. if no fast link pulses (flps) are detected and normal link pulses (nlps) are detected, the 82555 defaults to 10 mbps operation. if the 82555 detects a speed change, it dynamically changes its transmit clock and receive clock frequencies to the appropriate value. this change takes a maximum of five milliseconds. 4.7 adapter mode addresses in dte (adapter) mode, the 82555 supports addresses 0, 1, 2, and 3 through the pins phya1 and phya0. four addresses are sufficient in the case of a combination adapter having three phys. for switch applications, the t4adv signal should be de-asserted to allow all 32 addresses to be available in repeater mode. figure 8. combination card example common magnetics pci bus 82557 fdx_n phy-t4 82555 t4 adv mii listat_n slave_tri 3669 82555 networking silicon 20 datasheet datasheet 21 networking silicon 82555 5.0 10base-t functionality in adapter mode 5.1 10base-t transmit clock generation the 20 mhz and 10 mhz clocks needed for 10base-t are synthesized from the external 25 mhz crystal or oscillator. the 82555 provides the transmit clock and receive clock to the mac at 2.5 mhz. 5.2 10base-t transmit blocks 5.2.1 10base-t manchester encoder after the 2.5 mhz clocked data is serialized in a 10 mbps serial stream, the 20 mhz clock performs the manchester encoding. the manchester code always has a mid-bit transition. if the value is 1b then the transition is from low to high. if the value is 0b then the transition is from high to low. the boundary transition occurs only when the data changes from bit to bit. for example, if the value is 10b, then the change is from high to low; if 01b, then the change is from low to high. 5.2.2 10base-t driver and filter since 10base-t and 100base-tx have different filtration needs, both filters are implemented inside the chip. this allows the two technologies to share the same magnetics. the 82555 supports both technologies through one pair of transmit differential pins and by externally sharing the same magnetics. in 10 mbps mode, the 82555 begins transmitting the serial manchester bit stream within 3 bit times (300 nanoseconds) after the mac asserts txen. in 10 mbps mode the line drivers use a pre- distortion algorithm to improve jitter tolerance. the line drivers reduce their drive level during the second half of wide (100 ns) manchester pulses and maintain a full drive level during all narrow (50 ns) pulses and the first half of the wide pulses. this reduces line overcharging during wide pulses, a major source of jitter. 5.3 10base-t receive blocks 5.3.1 10base-t manchester decoder the 82555 performs manchester decoding and timing recovery when in 10 mbps mode. the manchester encoded data stream is decoded from the receive differential pair to separate receive clock and receive data lines from the differential signal. this data is transferred to the controller at 2.5 mhz/nibble through the mii. the high-performance circuitry of the 82555 exceeds the ieee 802.3 jitter requirements. 5.3.2 10base-t twisted pair ethernet (tpe) receive buffer and filter in 10 mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. the filter is implemented inside the 82555 for supporting single magnetics that are shared with the 100base-tx side. the input differential voltage range for the 82555 networking silicon 22 datasheet twisted pair ethernet (tpe) receiver is greater than 585 mv and less than 3.1 v. the tpe receive buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the requirements of the 10base-t standard. the following line activity is determined to be inactive and is rejected: ? differential pulses of peak magnitude less than 300 mv. ? continuous sinusoids with a differential amplitude less than 6.2 v pp and frequency less than 2 mhz. ? sine waves of a single cycle duration starting with 0 or 180 phase that have a differential amplitude less than 6.2 v pp and a frequency of at least 2 mhz and not more than 16 mhz. these single-cycle sine waves are discarded only if they are preceded by 4 bit times (400 nanoseconds) of silence. all other activity is determined to be either data, link test pulses, auto-negotiation fast link pulses, or the idle condition. when activity is detected, the carrier sense signal is asserted to the mac. 5.3.3 10base-t error detection and reporting in 10 mbps mode, the 82555 can detect errors in the receive data. the following condition is considered an error: the receive pairs voltage level drops to the idle state during reception before the end-of-frame bit is detected (250 nanoseconds without mid-bit transitions). 5.4 10base-t collision detection collision detection in 10 mbps mode is indicated by simultaneous transmission and reception. if the 82555 detects this condition, it asserts a collision indication to the controller. 5.5 10base-t link integrity the link integrity in 10 mbps works with link pulses. the 82555 senses and differentiates those link pulses from fast link pulses and from 100base-tx idles. in the first and last case, the 82555 activates parallel detection of the respective technology; and in the second case, auto-negotiation. the 10 mbps link pulses or normal link pulses are driven in the transmit differential pair line but are 100 ns wide and have levels from 0 v to 5 v. the link beat pulse is also used to determine if the receive pair polarity is reversed. if it is, the polarity is corrected internally. 5.6 10base-t jabber control function the 82555 contains a jabber control function that inhibits transmission after a specified time window when enabled. in 10 mbps mode, the jabber timer is set to a value between 26.2 ms and 39 ms. if the 82555 detects continuous transmission that is greater than this time period, it prevents further transmissions from onto the wire until it detects that the mac transmit enable signal has been inactive for at least 314 ms. datasheet 23 networking silicon 82555 5.7 10base-t full duplex the 82555 supports 10 mbps full duplex by disabling the collision function, the squelch test, and the carrier sense transmit function. this allows the 82555 to transmit and receive simultaneously, achieving up to 20 mbps of network bandwidth. the configuration can be achieved through auto- negotiation. full duplex should only be used in point-to-point connections (no shared media). flow control is always disabled. 82555 networking silicon 24 datasheet datasheet 25 networking silicon 82555 6.0 repeater mode the 82555 has a compete set of repeater features making it the ideal phy for class 1 (mii) repeater designs. the 82555 works in repeater mode when the rpt signal (pin 50) is high. the frc100 signal (pin 51) determines which type of repeater is supported, either 100base-tx or 10base-t. 6.1 special repeater features special features of the 82555 repeater mode operation include: ? fully ieee compliant with automatic carrier disconnect. the 82555 will disconnect when it receives false carrier detects. either a long series of valid idle symbols or a valid jk pair will cause it to reconnect. ? narrow 14 mm analog side that enables tight packing of multiple phys, which is ideal for 8, 12, 18, 24, or even 32 port repeater designs. ? very low emissions and high noise immunity. ? 32 configurable addresses through five address lines. ? auto-negotiation disable function. in repeater mode, the auto-negotiation function is not used for configuration purposes. when auto-negotiation is enabled in repeater mode, the mii management will be able to obtain data from the mdi auto-negotiation register about the remote partner. this is a feature for hub management allowing a 10/100 mbps repeater design to automatically detect whether or not it can operate at 100 mbps. if the andis signal is de-asserted, the auto-negotiation feature will be disabled. ? forced 10 mbps or 100 mbps operation (allows for a 10/100 repeater design). ? receive port enable function. the porten signal is a glueless interface to the repeater interface controller (ric). when the porten signal is low, all receive signals are tri-stated, except crs and col. ? 26-bit phy budget for round trip. the total phy bit budget is 8 bits from the mii to the wire and 18 bits from the wire to the mii. ? static 2.5 mhz (10base-t) or 25 mhz (100base-tx) clock input for repeater designs (issued by ric). the 82555 clock source is fixed between resets. there is one input, either 2.5 mhz or 25 mhz, as indicated by the level at the frc100 pin. all clocks have a common source generation so the that ppm is 0 between them (x1, 2.5 mhz and 25 mhz). ? dte (adapter) features not available in repeater mode: full duplex, flow control, and the combination auto-negotiation interface for t4. 6.2 connectivity a 25 mhz buffered oscillator can provide the clock to all of the 82555 devices. a 2.5 mhz (10 mbps) or a 25 mhz (100 mbps) signal is required to clock the ric and the txc signal in the phys. txd[3:0], txerr, rxc, rxd[3:0], rxdv, and rxerr are single-bus (shortened) for all 82555 networking silicon 26 datasheet phys connected to the ric. signals txen, crs, and porten are connected from each of the 82555 devices to the specified ric pin. the figure below illustrates an example of multiple 82555s connected to a 25 mhz (or 2.5 mhz) oscillator. figure 9. clock signal example x1 txclk clk ric phy1 phy2 phy3 x1 x1 txclk txclk pc-3691 2.5/25 mhz (10/100) 2.5/25 mhz (10/100) datasheet 27 networking silicon 82555 7.0 management data interface the 82555 provides status and accepts management information through the management data interface (mdi). this is accomplished through read and write operations to various registers in accordance with the ieee 802.3u mii specification. 7.1 mdi frame structure data read from or written to a particular register is called a management frame and is sent serially over the mdio pin synchronously to the mdc signal. read and write cycles are viewed from the perspective of the controller. thus, the controller always drives the start, opcode, phy address, and register address onto the mdio pin. for read cycles, the controller drives the transition bits and data onto the mdio pin; for write cycles, to the 82555. the controller drives addresses and data on the falling edge of the mdc signal, and the 82555 latches the data on the rising edge of the mdc signal. the following list defines protocol terms: preamble at the beginning of each transaction, the controller send a sequence of 32 contiguous logic one bits on the mdio pin with corresponding cycles on the mdc pin for synchronization by the 82555. st this field contains the value of 01b indicating the start of a frame. op this is a 2-bit field containing one of the following two operation codes: 10b (read) or 01b (write). phyad this field is a 5-bit address of the 82555 device that provides support for 32 unique phy addresses. the controller drives the value written into the phyad portion of the mdi register in this field. regad this field is a 5-bit address of a specific register within the 82555. this provides support for 32 unique registers. the desired register address is specified by the value written to the mdi register. ta this field contains a 2-bit value specifying the period during a read cycle that no device may actively drive the mdio signal. during a read transaction, the 82555 should not drive the mdio signal in the first bit time; however, it will drive a 0b in the second bit time. during a write transaction, the controller drives the pattern of 10b to fill this time. data this field contains 16 bits of data driven by the 82555 on a read transaction or by the controller on a write transactions. this data is either control or status parameters passed between the controller and the 82555. idle during the idle state, the mdio signal is in a high impedance state. the mdio driver is disabled, and the 82555 will pull the mdio signal high to a logic 1. 82555 networking silicon 28 datasheet the 82555 address can be configured to four 0 through 3 in dte (adapter) mode and 0 through 31 in repeater mode. a special functions for switches allows 32 addresses to exist in repeater mode. the management frame structure is as follows: 7.2 mdi registers mdi registers are described in the following subsections and the acronyms mentioned in the registers are defined as follows: sc - self cleared. ro -read only. p- external pin affects 82555 register content. ll - latch low. lh - latch high. 7.2.1 mdi registers 0 - 7 7.2.1.1 register 0: control register bit definitions transition st op phyad regad ta data read <01> <10> datasheet 29 networking silicon 82555 7.2.1.2 register 1: status register bit definitions 11 power-down this bit sets the 82555 into a low power mode. 1 = power-down enabled 0 = power-down disabled (normal operation) 0rw 10 isolate this bit allows the 82555 to electrically isolate the media independent interface. when the mii is isolated, the 82555 does not respond to txd[3:0], txen, and txerr input signals. also, the 82555 presents high impedance on its txc, rxc, rxdv, rxerr, rxd[3:0], col, and crs output signals. in the tx mode, the 82555 responds to management transactions. 1 = electrically isolate mii 0 = normal operation 0rw 9 restart auto- negotiation this bit restarts the auto-negotiation process and is self- clearing. 1 = restart auto-negotiation process 0 = normal operation 0rw sc 8 duplex mode this bit controls the duplex mode when auto-negotiation is disabled. if the 82555 reports that it is only able to operate in one duplex mode, the value of this bit shall correspond to the mode which the 82555 can operate. when the 82555 is placed in loopback mode, the behavior of the phy shall not be affected by the status of this bit, bit 8. 1 = full duplex 0 = half duplex 0rw 7 collision test this bit will force a collision in response to the assertion of the transmit enable signal. 1 = force col 0 = do not force col 0rw 6:0 reserved these bits are reserved and should be set to 0000000b. 0 rw bit(s) name description default r/w 15 100base-t4 1 = 82555 able to perform 100base-t4 0 = 82555 not able to perform 100base-t4 -- ro p 14 100base-tx full duplex 1 = 82555 able to perform full duplex 100base-tx 0 = 82555 not able to perform full duplex in repeater mode -- ro p 13 100 mbps half duplex 1 = 82555 able to perform half duplex 100base-tx 0 = 82555 not able to perform 100base-tx -- ro p 12 10 mbps full duplex 1 = 82555 able to operate at 10 mbps in full duplex mode 0 = 82555 not able to operate in full duplex mode in 10base-t -- ro p 11 10 mbps half duplex 1 = 82555 able to operate at 10 mbps in half duplex mode 0 = 82555 not able to operate in 10base-t -- ro p 10:7 reserved these bits are reserved and should be set to 0000b. 0 ro bit(s) name description default r/w 82555 networking silicon 30 datasheet 7.2.1.3 register 2: 82555 identifier register bit definitions 7.2.1.4 register 3: 82555 identifier register bit definitions 7.2.1.5 register 4: auto-negotiation advertisement register bit definitions 6 management frames preamble suppression 1 = 82555 will accept management frames with preamble suppressed 0 = 82555 will not accept management frames with preamble suppressed -- ro 5 auto-negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process has not completed 0ro 4 remote fault 1 = remote fault condition detected 0 = no remote fault condition detected 0ro p 3 auto-negotiation ability 1 = 82555 is able to perform auto-negotiation 0 = 82555 is in repeater mode and auto-negotiation disable pin is high 1ro 2 link status 1 = valid link has been established 0 = invalid link detected 0ro ll sc 1 jabber detect 1 = jabber condition detected 0 = no jabber condition detected 0ro lh sc 0 extended capability 1 = extended register capabilities enabled 0 = no extended register capabilities 1ro bit(s) name description default r/w 15:0 82555 id (high byte) value: 02a8h -- ro bit(s) name description default r/w 15:0 82555 id (low byte) value: 0150h -- ro bit(s) name description default r/w 15 next page constant 0 = transmitting primary capability data page -- ro 14 reserved this bit is reserved and should be set to 0b. 0 ro 13 remote fault 1 = indicate link partners remote fault 0 = no remote fault 0rw 12:5 technology ability field technology ability field is an 8-bit field containing information indicating supported technologies specific to the selector field value. -- rw 4:0 selector field the selector field is a 5-bit field identifying the type of message to be sent via auto-negotiation. this field is read only in the 82555 and contains a value of 00001b, ieee standard 802.3. 00001 ro bit(s) name description default r/w datasheet 31 networking silicon 82555 7.2.1.6 register 5: auto-negotiation link partner ability register bit definitions 7.2.1.7 register 6: auto-negotiation expansion register bit definitions 7.2.2 mdi registers 8 - 15 registers eight through fifteen are reserved for ieee. 7.2.3 mdi registers 16 - 31 register numbers 16, 17, 20, 21, 22, 23, 24, 25, and 27 are described in the following subsections. bit(s) name description default r/w 15 next page this bit reflects the 82555s link partners auto- negotiation ability. -- ro 14 acknowledge this bit is used to indicate that the 82555 has successfully received its link partners auto- negotiation advertising ability. -- ro 13 remote fault this bit reflects the 82555s link partners auto- negotiation ability. -- ro 12:5 technology ability field this bit reflects the 82555s link partners auto- negotiation ability. -- ro 4:0 selector field this bit reflects the 82555s link partners auto- negotiation ability. -- ro bit(s) name description default r/w 15:5 reserved these bits are reserved and should be set to a constant 0. 0ro 4 parallel detection fault 1 = fault detected via parallel detection (multiple link fault occurred) 0 = no fault detected via parallel detection this bit will self-clear on read 0ro sc lh 3 link partner next page able 1 = link partner is next page able 0 = link partner is not next page able 0ro 2 next page able 1 = local drive is next page able 0 = local drive is not next page able 0ro 1 page received 1 = new page received 0 = new page not received this bit will self-clear on read. 0ro sc lh 0 link partner auto- negotiation able 1 = link partner is auto-negotiation able 0 = link partner is not auto-negotiation able 0ro 82555 networking silicon 32 datasheet 7.2.3.1 register 16: 82555 status and control register bit definitions 7.2.3.2 register 17: 82555 special control bit definitions bit(s) name description default r/w 15 flow control this bit enables phy base (bay technologies) flow control. 1 = enable phy base flow control 0 = disable phy base flow control 0rw 14 reserved these bits are reserved and should be set to 0b 0 rw 13 carrier sense disconnect control this bit enables the disconnect function. 1 = disconnect function enabled (default in dte) 0 = disconnect function disabled (default in repeater) 0 (dte 1 (rptr) rw 12 transmit flow control disable this bit enables transmit flow control 1 = transmit flow control enabled 0 = transmit flow control disabled 0rw 11 receive de- serializer in-sync indication this bit indicates status of the 100base-tx receive de-serializer in-sync. -- ro 10 100base-tx power-down this bit indicates the power state of 100base-tx 82555. 1 = power-down 0 = normal operation -- ro 9 10base-t power-down this bit indicates the power state of 10base-tx 82555. 1 = power-down 0 = normal operation -- ro 8 polarity this bit indicates 10base-t polarity. 1 = reverse polarity 0 = normal polarity -- ro 7:3 reserved these bits are reserved and should be set to a constant 0. 00000 ro 2 t4 this bit indicates the auto-negotiation result. 1 = 100base-t4 0 = no 100base-t4 -- ro 1 speed this bit indicates the auto-negotiation result. 1 = 100 mbps 0 = 10 mbps -- ro 0 duplex mode this bit indicates the auto-negotiation result. 1 = full duplex 0 = half duplex -- ro bit(s) name description default r/w 15 scrambler by- pass 1 = by-pass scrambler 0 = normal operations 0rw 14 by-pass 4b/5b 1 = 4 bit to 5 bit by-pass 0 = normal operation 0rw datasheet 33 networking silicon 82555 7.2.3.3 register 20: 100base-tx receive disconnect counter bit definitions 7.2.3.4 register 21: 100base-tx receive error frame counter bit definitions 13 force transmit h- pattern 1 = force transmit h-pattern 0 = normal operation 0rw 12 force 34 transmit pattern 1 = force 34 transmit pattern 0 = normal operation 0rw 11 good link 1 = 100base-tx link good 0 = normal operation 0rw 10 reserved this bit is reserved and should be set to 0b. 0 rw 9 transmit carrier sense disable 1 = transmit carrier sense disabled 0 = transmit carrier sense enabled 0rw 8 disable dynamic power-down 1 = dynamic power-down disabled 0 = dynamic power-down enabled (normal) 0rw 7 auto-negotiation loopback 1 = auto-negotiation loopback 0 = auto-negotiation normal mode 0rw 6 mdi tri-state 1 = mdi tri-state (transmit driver tri-states) 0 = normal operation 0rw 5 filter by-pass 1 = by-pass filter 0 = normal filter operation 0rw 4 auto polarity disable 1 = auto polarity disabled 0 = normal polarity operation 0rw 3 squelch disable 1 = 10base-t squelch test disable 0 = normal squelch operation 0rw 2 extended squelch 1 = 10base-t extended squelch control enabled 0 = 10base-t extended squelch control disabled -- rw 1 link integrity disable 1 = link disabled 0 = normal link integrity operation 0rw 0 jabber function disable 1 = jabber disabled 0 = normal jabber operation 0rw bit(s) name description default r/w 15:0 disconnect event this field contains a 16-bit counter that increments for each disconnect event. the counter stops when full (and does not roll over) and self-clears on read in repeater mode, a frame that starts without jk is a disconnect event. -- ro sc bit(s) name description default r/w 15:0 receive error frame this field contains a 16-bit counter that increments once per frame for any receive error condition (such as a symbol error or premature end of frame) in that frame. the counter stops when full (and does not roll over) and self-clears on read. -- ro sc bit(s) name description default r/w 82555 networking silicon 34 datasheet 7.2.3.5 register 22: receive symbol error counter bit definitions 7.2.3.6 register 23: 100base-tx receive premature end of frame error counter bit definitions 7.2.3.7 register 24: 10base-t receive end of frame error counter bit definitions 7.2.3.8 register 25: 10base-t transmit jabber detect counter bit definitions 7.2.3.9 register 27: 82555 special control bit definitions bit(s) name description default r/w 15:0 symbol error counter this field contains a 16-bit counter that increments for each symbol error. the counter stops when full (and does not roll over) and self-clears on read. in a frame with a bad symbol, each sequential six bad symbols count as one. -- ro sc bit(s) name description default r/w 15:0 premature end of frame this field contains a 16-bit counter that increments for each premature end of frame event. the counter stops when full (and does not roll over) and self-clears on read. a frame without a tr at the end is considered a premature end of frame event. -- ro sc bit(s) name description default r/w 15:0 end of frame counter this is a 16-bit counter that increments for each end of frame error event. the counter stops when full (and does not roll over) and self-clears on read. -- ro sc bit(s) name description default r/w 15:0 jabber detect counter this is a 16-bit counter that increments for each jabber detection event. the counter stops when full (and does not roll over) and self-clears on read. -- ro sc bit(s) name description default r/w 15:3 reserved these bits are reserved and should be set to 0b. 0 rw 2:0 led switch control value 000 001 010 011 100 101 110 111 actled activity speed speed activity off off on on liled link collision link collision off on off on 000 rw datasheet 35 networking silicon 82555 8.0 auto-negotiation functionality the 82555 supports auto-negotiation. auto-negotiation is a scheme of auto-configuration designed to manage interoperability in multifunctional lan environments. it allows two stations with n different modes of communication to establish a common mode of operation. at power- up, auto-negotiation automatically establishes a link that takes advantage of an auto-negotiation capable device. an auto-negotiation capable device can detect and automatically configure its port to take maximum advantage of common modes of operation without user intervention or prior knowledge by either station. the possible common modes of operation are: 100base-tx, 100base-tx full duplex, 100base-t4, 10base-t, and 10base-t full duplex. 8.1 description auto-negotiation selects the fastest operating mode (in other words, the highest common denominator) available to hardware at both ends of the cable. a phys capability is encoded by bursts of link pulses called fast link pulses (flps). connection is established by flp exchange and handshake during link initialization time. once the link is established by this handshake, the native link pulse scheme resumes (that is, 10base-t or 100base-tx link pulses). a reset or management renegotiate command (through the mdi interface) will restart the process. to enable auto-negotiation, bit 12 of the mdi control register must be set. if the 82555 cannot perform auto-negotiation, it will set this bit to 0b and determine the speed using parallel detection. the 82555 supports four technologies: 100base-tx full and half duplex and 10base-t full and half duplex. since only one technology can be used at a time (after every renegotiate command), a prioritization scheme must be used to ensure that the highest common denominator ability is chosen. table 4 lists the technology ability field bit assignments. each bit in this table is set according to what the phy is capable of supporting. in the case of the 82555, bits 0, 1, 2, and 3 are set. table 5 lists the priority of each of the technologies. table 4. technology ability field bit assignments bit setting technology 0 10base-t half duplex 1 10base-t full duplex 2 100base-t half duplex 3 100base-t full duplex 4 100base-t4 5 pause (flow control) 6 reserved 7 reserved table 5. technology priority priority technology 1 100base-tx full duplex 2 100base-t4 3 100base-tx half duplex 82555 networking silicon 36 datasheet to detect the correct technology, the two register fields should be anded together to obtain the highest common denominator. this value should then be used to map into a priority resolution table used by the mac driver to use the appropriate technology. the following is an outline of the auto-negotiation process: 1. receive 3 consecutive, matching code words 2. set acknowledge bit in transmit code word 3. receive 3 consecutive, matching code words with acknowledge bit set 4. transmit 6 to 8 more code words with acknowledge bit set 5. determine operating mode via the priority table 6. receive flp from the link partner and record flp in the mii register 8.2 parallel detect and auto-negotiation the 82555 automatically determines the speed of the link either by using parallel detect or auto- negotiation. upon a reset, a link status fail, or a negotiate/renegotiate command, the 82555 inserts a long delay during which no link pulses are transmitted. this period, known as force_fail, insures that the 82555s link partner has gone into a link fail state before auto-negotiation or parallel detection begins. thus, both sides (the 82555 and the 82555s link partner) will perform auto- 4 10base-t full duplex 5 10base-t half duplex table 5. technology priority priority technology datasheet 37 networking silicon 82555 negotiation or parallel detection with no data packets being transmitted. connection is then established either by flp exchange or parallel detection. the 82555 will look for both flps and link integrity pulses. the following diagram illustrates this process. figure 10. auto-negotiation and parallel detect force_fail ability detect either by parallel detect or auto- negotiation. 10base-t or 100base-tx link ready flp capable link pass parallel detection auto-negotiation look at link pulse; auto-negotiation capable = 0 auto-negotiation capable = 1 ability match auto-negotiation complete bit set 82555 networking silicon 38 datasheet datasheet 39 networking silicon 82555 9.0 led descriptions the 82555 supports four led pins to indicate link status, network activity and network speed. ? link : this led is off (logic high) until a valid link has been detected. after a valid link has been detected, the led will remain on (active-low). ? activity : this led is on (active-low) when activity is detected on the wire. in dte (adapter) mode, this led is on during transmit and receive when the 82555 is not in loopback mode. in repeater mode, this led is on only during receive when the 82555 is not in loopback mode. ? speed : this led will be on if a 100base-tx link is detected and off if a 10base-t link is detected. if the link fails while in auto-negotiation, this led will keep the last valid link state. if 100base-tx link is forced this led will be on, regardless of the link status. this led will be of if the 10base-t link is forced, regardless of the link status. ? full duplex: the fdx_n signal can operate as a led if it is enabled. it indicates full duplex link for either 100base-tx or 10 base-t technology. mdi register 27 in section 7.2.3.9, register 27: 82555 special control bit definitions on page 34 details the information for led function mapping and support enhancements. 82555 networking silicon 40 datasheet datasheet 41 networking silicon 82555 10.0 reset and miscellaneous test modes 10.1 reset when the 82555 reset signal is asserted (high), all internal circuits are reset. txc and rxc should run continuously even though reset is active. the 82555 may also be reset through the mdi reset bit. 10.2 loopback when the loopback pin is being driven high, the 82555 executes a loopback diagnostics operation. this mode can also be accessed through the mdi registers. 10.3 scrambler bypass when the scrambler bypass pin is active, the 82555 bypasses the scrambler/descrambler. this mode can also be accessed through the mdi registers. 10.4 test port when the testen pin is high, the test pins provide a test access port for the 82555. in test mode, the 82555 will default to address 1. the 82555 has a simple test access port (tap) from which all the test modes are selected and test instructions are operated. the tap is controlled by a simple mechanism and handshake. activation of all test modes requires simple hardware. the tap signals connected to the 82555 blocks and periphery control the 82555s mode of operation to allow simple testing and internal built-in self testing. the test instruction are shifted into the test instruction shift register (tisr) through the tin pin. the tin pin is sampled on the rising edge of the tck input signal. the instruction is transferred from the tisr to the test instruction register (tir) when testen is sampled high on the rising edge of tck. as a general rule, all the tap input and output pins are activated by the rising edge of tck. if tck is a constant clock signal, then testen must be 1 clock pulse width. when the tir receives a new instruction, the instruction is decoded into control signals and synchronized to the 10 mhz clock. these control signals set the 82555 blocks into various test modes. in order to achieve stable synchronization between the clock signal (x1) and the tck signal, the tck input signal frequency should be less than or equal to half of the clock input signal frequency. 82555 networking silicon 42 datasheet the tout pin is controlled by different sources according to the active test instruction. the tout signal is activated by the falling edge of tck. the tap must be reset during power-up. otherwise, the 82555 can wake-up during high-z mode or nand test, which can be harmful to the board. the tap should be reset only with a hardware reset input pin and not with software reset. the tout control logic selects the tisr output in all tests, except burn-in test modes. table 6. test instruction coding number code test instruction select input to tout 1 00000 idle tisr d4out 2 00001 reserved tisr d4out 3 00010 high-z high-z 4 00011 nand test tisr d4out datasheet 43 networking silicon 82555 11.0 electrical specifications and timing parameters 11.1 absolute maximum ratings 11.2 general operating conditions 11.3 dc characteristics 11.3.1 mii dc characteristics 11.3.2 10base-t voltage/current dc characteristics symbol parameter description min typ max units t c case temperature under bias 0 85 c t s storage temperature -65 140 c v sup supply voltage -0.5 7.0 v v oa a a. stresses above the listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ex- posure to absolute maximum rating conditions for extended periods may affect device reliability. all output voltages -0.5 7.0 v v otd transmit data output voltage -0.5 8.0 v v ia all input voltages -1.0 6.0 v symbol parameter description min typ max units v cc supply voltage 4.75 5.25 v t c case temperature 0 85 c symbol parameter description condition min typ max units v il input low voltage (ttl) 0 0.8 v v ih input high voltage (ttl) 2.0 v v ol output low voltage i out = 4 ma 0.45 v v oh output high voltage i out = -4 ma 2.4 v i il input low leakage current 0 < v in < v cc 15 m a c in a a. this parameter is only characterized, not tested. it is valid for digital pins only. input capacitance 10 pf symbol parameter description condition min typ max units r id10 a input differential resistance dc and v rdp = (v cc /2) + 0.5 v 10 k w 82555 networking silicon 44 datasheet 11.3.3 100base-tx voltage/current dc characteristics v ida10 input differential accept voltage 5 mhz f 10 mhz 585 3100 mv p v idr10 input differential reject voltage 5 mhz f 10 mhz 300 mv p v icm10 input common mode voltage v cc /2 v v od10 output differential voltage rl = 100 w b rbias10 = 768 w 2.2 2.8 v i cct10 c line driver supply rbias10 = 768 w 110 ma i cc10 d current on all v cc pins 120 ma i cct10tot total supply current 230 ma l ila10 e leakage on analog pins 20 ma a. this value is measured across the receive differential pins, rdp and rdn. b. rl is the resistive load across the receive differential pins, rdp and rdn. c. transmitter current is measured with a 1:1 transformer on the center tap. d. current is measured on all v cc pins at v cc = 5.25 v. e. the analog pins are: tdp, tdn, rdp, rdn, rbias10, and rbias100. symbol parameter description condition min typ max units figure 11. rbias10 resistance versus i cct10 805 w 768 w 735 w 105ma 110ma 115ma icct10 rbias10 symbol parameter description condition min typ max units r id100 input differential resistance dc v rdp = (v cc /2) + 0.5 v v rdn = (v cc /2) - 0.5 v 10 k w v ida100 input differential accept voltage 500 mv p v idr100 input differential reject voltage 100 mv p v icm100 input common mode voltage v cc /2 v v od100 a output differential voltage rbias100 = 634 w 0.95 1.00 1.05 v p i cct100 b line driver supply rbias100 = 634 w 40 ma datasheet 45 networking silicon 82555 11.4 ac characteristics 11.4.1 mii clock specifications i cc100 c current on all v cc pins 235 ma i cct100tot total supply current 275 ma a. transmitter current is measured with a 1:1 transformer on the center tap. b. transmitter current is measured with a 1:1 transformer on the center tap. c. current is measured on all v cc pins at v cc = 5.25 v. symbol parameter description condition min typ max units figure 12. rbias100 resistance versus i cct100 667 w 634 w 604 w 38ma 40ma 42ma icct100 rbias100 figure 13. ac testing level conditions output levels input levels v ih = 2.0 v v il = 0.8 v v ol = 0.45 v v oh = 2.4 v symbol parameter conditions min typ max units t1 t p100 txc/rxc period 100 mbps 40 ns t2 t p10 txc/rxc period 10 mbps 400 ns t3 t pmdc mdc clock period 400 ns t4 t txdc txc duty cycle 35 65 % t5 t rxdc rxc duty cycle 35 65 % t6 t mdc mdc duty cycle 35 65 % 82555 networking silicon 46 datasheet 11.4.2 mii timing parameters figure 14. mii clocks ac timing t1,t2,t3 1.5v t4,t5,t6 t4,t5,t6 symbol parameter conditions min typ max units t7 t txdv txd[3:0], txen, txerr setup from the rising edge of txc 15 25 ns t8 t txh txd[3:0], txen, txerr hold time after the rising edge of txc 0ns t9 t rxsu rxd[3:0], rxdv, rxerr valid before the rising edge of rxc 10 ns t10 t rxh rxd[3:0], rxdv, rxerr hold time after the rising edge of rxc 10 ns t11 t msu mdio setup time to the rising edge of mdc mdio input 10 ns t12 t mh mdio hold time from the rising edge of mdc mdio input 10 ns t13 t mv mdio valid from the rising edge of mdc mdio output 300 ns figure 15. mii transmit timing parameters t7 t8 txclk txd[3:0], txer,txen data invalid data invalid data valid datasheet 47 networking silicon 82555 11.4.3 repeater mode timing parameters figure 16. mii receive timing parameters figure 17. mii timing parameters: mdc/mdio t9 t10 rxclk rxd[3:0], rxer,rxdv data invalid data invalid data valid t11 t12 mdc mdio (input) data invalid data invalid data valid t13 mdio (output) data invalid data invalid data valid symbol parameter conditions min typ max units t14 t rdrv porten assertion to rxd[3:0], rxdv, and rxerr (rxc driven) 1.5 2.5 rxc clocks t15 t rtst porten de-assertion to rxd[3:0], rxdv, and rxerr (rxc tri-stated) a a. rxc, rxdv, and rxerr are tri-stated only after they have been driven low (0). 1.5 2.5 rxc clocks figure 18. port enable timing t14 t15 porten rxd[3:0], rxer,rxdv, rxclk si g nal driven 82555 networking silicon 48 datasheet 11.4.4 transmit packet timing parameters 11.4.5 squelch test timing parameters symbol parameter conditions min typ max units t15 t xen_st txc on first txen active to start of frame 100 mbps 10 12 bits t15a t xen_st txc on first txen active to start of frame 10 mbps 3.5 5 bits t16 t xen_crsh txc on first txen active to rising edge of crs 100 mbps 4 bits t16a t xen_crsh txc on first txen active to rising edge of crs 10 mbps 1.5 bits t17 t xen_end txc on first txen inactive to end of frame 100 mbps 17 bits t17a t xen_end txc on first txen inactive to end of frame 10 mbps 5 bits t18 t xen_crsl txc on first txen inactive to falling edge of crs 100 mbps 11 bits t18a t xen_crsl txc on first txen inactive to falling edge of crs 10 mbps 6 bits t19 t eof end of frame high time 10 mbps 250 350 ns figure 19. transmit frame timing parameters txen crs valid frame data txclk frame on link t15,t15a t16,t16a t17,t17a t18,t18a symbol parameter conditions min typ max units t20 t sqe_del collision detect heartbeat delay 10 mbps 7 8 bits t21 t sqe_dur collision detect heartbeat duration 10 mbps 9 11 bits datasheet 49 networking silicon 82555 11.4.6 jabber timing parameters 11.4.7 receive packet timing parameters figure 20. squelch test timing parameters txen col txclk t20 t21 symbol parameter conditions min typ max units t22 t jab_on jabber turn-on delay (txen asserted to end of transmit frame) 10 mbps 26 ms t23 t jab_off jabber turn-off delay (txen de- asserted to falling edge of col) 10 mbps 410 ms figure 21. jabber timing parameters txen col tdp/tdn t22 t23 symbol parameter conditions min typ max units t24 t r_crsh start of receive frame to rising edge of crs 100 mbps 11 13 bits t24a t r_crsh start of receive frame to rising edge of crs 10 mbps 3 5 bits t25 t r_rxdvh start of receive frame to rising edge of rxdv 100 mbps 15 bits t25a t r_rxdvh start of receive frame to rising edge of rxdv 10 mbps 22 bits t26 t r_crsl end of receive frame to falling edge of crs 100 mbps 14 16 bits 82555 networking silicon 50 datasheet 11.4.8 10base-t normal link pulse (nlp) timing parameters 11.4.9 auto-negotiation fast link pulse (flp) timing parameters t26a t r_crsl end of receive frame to falling edge of crs 10 mbps 4.5 bits t27 t r_rxdvl end of receive frame to falling edge of rxdv 100 mbps 12 bits t27a t r_rxdvl end of receive frame to falling edge of rxdv 10 mbps 4 bits symbol parameter conditions min typ max units figure 22. receive packet timing parameters rxdv crs valid frame data rxclk frame on link t25,t25a t24,t24a t26,t26a t27,t27a symbol parameter conditions min typ max units t28 t nlp_wid nlp width 10 mbps 100 ns t29 t nlp_per nlp period 10 mbps 8 24 ms figure 23. normal link pulse timing parameters normal link pulse t29 t28 symbol parameter conditions min typ max units t30 t flp_wid flp width (clock/data) 100 ns t31 t flp_clk_clk clock pulse to clock pulse period 111 125 139 m s t32 t flp_clk_dat clock pulse to data pulse period 55.5 62.5 69.5 m s datasheet 51 networking silicon 82555 11.4.10 reset timing parameters 11.4.11 x1 clock specifications t33 t flp_bur_num number of pulses in one burst 17 33 t34 t flp_bur_wid flp burst width 2 ms t35 t flp_bur_per flp burst period 8 24 ms symbol parameter conditions min typ max units figure 24. fast link pulse timing parameters fast link pulse t31 t30 t30 clock pulse data pulse clock pulse flp bursts t34 t35 symbol parameter conditions min typ max units t36 t rst_wid reset pulse width 500 ns t37 t pup_rst power-up to falling edge of reset 500 m s figure 25. reset timing parameters power up ( vcc ) reset t37 t36 symbol parameter conditions min typ max units t38 t x1_dc x1 duty cycle 40 60 % t39 t x1_pr x1 period 50 ppm 40 ns 82555 networking silicon 52 datasheet 11.4.12 100base-tx transmitter ac specification figure 26. x1 clock specifications t38 2.5v t39 t39 0.4v 4.0v symbol parameter conditions min typ max units t40 t jit tdp/tdn differential output peak jitter hls data 300 700 ps datasheet 53 networking silicon 82555 12.0 82555 package information this section provides the physical packaging information for the 82555. the 82555 is an 100-pin plastic quad flat pack (qfp) device. package attributes are provided in table 7 and the dimensions are shown in figure 27 . figure 27. dimension diagram for the 82555 qfp table 7. dimensions for the 82555 qfp symbol description min norm max n lead count - 100 - a overall height - - 3.15 a1 stand off 0.05 - 0.40 b lead width 0.20 0.30 0.40 c lead thickness 0.10 0.15 0.20 d terminal dimension 17.5 17.9 18.3 d1 package body - 14.0 - e terminal dimension 23.5 23.9 24.3 e1 package body - 20.0 - e1 lead pitch 0.53 0.65 0.77 l1 foot length 0.60 0.80 1.00 y d d1 e e1 eb a1 a c seating plane seating plane see detail a detail a t l1 pc-3712 82555 networking silicon 54 datasheet t lead angle 0.0 - 10.0 y coplanarity - - 0.10 table 7. dimensions for the 82555 qfp symbol description min norm max |
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